In the process of manufacturing semiconductors device, a plurality of circuit structures are usually manufactured on a wafer, then the wafer is cut and divided into a plurality of chips; each of the chips is disposed on a chip carrier or lead frame with bonding wires connecting the electrodes on the chip to the leads of the lead frame that are partially exposed through an encapsulation for external connection therefore providing various semiconductor package products. Alternatively solder bumps may be attached to the electrodes of the chip on wafer level and the wafer is then diced to singulate the chips, each solder-bumped chip is then flip-chip attached on a baseboard for connecting the electrodes to the external of encapsulation.
The encapsulation methods of prior arts include the steps of cutting the wafer to obtain the individual semiconductor elements first, then attaching each semiconductor element onto the base plate and connecting the electrodes of the semiconductor element through lead wire or flip chip bonding, and finally plastically packaging the semiconductor element. The wafer carrying the chips for encapsulation is cut first and then the electrodes of the semiconductor elements are connected and encapsulated; the manufacturing procedures of the encapsulation are manifold; and the single encapsulation of each semiconductor element enlarges the size of the encapsulation and increases the cost of manufacture, which is not suitable for the ever increasing demand of miniaturization and low cost for the hand held electronic device applications. Therefore a method to produce a wafer level chip scale package is needed.